6.16 System Interface Arbitration

System Interface Arbitration Rules

• If the System interface is in slave state, and a processor request or coherency data response is ready for issue, and the required resources are available (e.g. a free request number, SysRdRdy* asserted, etc.), the processor asserts SysReq*. The processor will not assert SysReq* unless all of the above conditions are met.
• The processor waits for the assertion of SysGnt*.
• When the processor observes the assertion of SysGnt* it negates SysReq* two SysClk cycles later. Once the processor asserts SysReq*, it does not negate SysReq* until the assertion of SysGnt*, even if the need for the System interface bus is contravened by an external coherency request.
• When the processor observes the assertion of SysRel*, it enters master state two SysClk cycles later, and begins to drive the System interface bus. SysRel* may be asserted coincidentally with or later than SysGnt*.
• Once in master state, the processor does not relinquish mastership of the System interface until it observes the negation of SysGnt*.
• The processor indicates it is relinquishing mastership of the System interface bus by asserting SysRel* for one SysClk cycle, two or more SysClk cycles after the negation of SysGnt*. The processor may issue any type of processor request or coherency data response in the two SysClk cycles following the negation of SysGnt*. This may delay the assertion of SysRel*.